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​​PyOpenCL for Xilinx FPGAs

​​For the Xilinx FPGA section check out the other document at ​+PyOpenCL with Altera FPGAs​ 

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​​Note: This flow is now almost working with PyOpenCL — need to figure out why the environment doesn’t exit nicely (leaves me with the correct output but a dead context).

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​​This is a continuation of the Altera experiments but redirected to the Xilinx environment. Thankfully, there is a single .so file libxilinxopencl.so that we need to link against per board! This vastly simplifies the linking framework withing PyOpenCL. 

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​​As before, we patch setup.py as follows:

​​default_libs = ["xilinxopencl"]

​​default_libdir = ["/opt/Xilinx/SDAccel/2016.1/runtime/lib/x86_64"]

​​default_incdir = ["/opt/Xilinx/SDAccel/2016.1/runtime/include"]

​​default_ldflags = []

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​​And, since I do not have an OpenCL-compatible Xilinx FPGA card, I tried to run this under emulation mode..

​​LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/opt/Xilinx/SDAccel/2016.1/runtime/lib/x86_64/ XILINX_SDACCEL=/opt/Xilinx/SDAccel/2016.1 XCL_EMULATION_MODE=true python -c "import pyopencl as cl; cl.get_platforms()"

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​​However, when calling cl.get_platforms()​ , PyOpenCL still fails! Now with an “unknown error” and OUT_OF_HOST_MEMORY signal code.

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​​unknown error

​​Traceback (most recent call last):

​​  File "<string>", line 1, in <module>

​​  File "/usr/local/lib/python2.7/dist-packages/pyopencl-2016.2-py2.7-linux-x86_64.egg/pyopencl/cffi_cl.py", line 589, in get_platforms

​​    _handle_error(_lib.get_platforms(platforms.ptr, platforms.size))

​​  File "/usr/local/lib/python2.7/dist-packages/pyopencl-2016.2-py2.7-linux-x86_64.egg/pyopencl/cffi_cl.py", line 564, in _handle_error

​​    raise e

​​pyopencl.cffi_cl.RuntimeError: clgetplatformids failed: OUT_OF_HOST_MEMORY

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​​Brilliant!

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​​Update 5th August 2016 @3:20pm — Xilinx SDAccel is intermittently working with the cl.get_platforms()​  call. Nothing particularly different about the environment except the following path setup.  (I think its the lnx64.o path that seems to make this work). To setup the Xilinx build environment for command-line compilation of OpenCL kernels, look at references: Forum Link, XUG PDF

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​​export XILINX_SDACCEL=/opt/Xilinx/SDAccel/2016.1

​​export XCL_EMULATION_MODE=true

​​export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/opt/Xilinx/SDAccel/2016.1/runtime/lib/x86_64

​​export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/opt/Xilinx/SDAccel/2016.1/lib/lnx64.o

​​export PATH=$PATH:/opt/Xilinx/SDAccel/2016.1/bin/

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​​To compile OpenCL kernels with SDAccel in software emulation mode, you need the following two commands. This is tied to the Alpha Data FPGA card, but you can check UG1023 for other supported cards. 

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​​# create emconfig.json that must be in your working directory

​​emconfigutil --xdevice xilinx:adm-pcie-7v3:1ddr:3.0 

​​# compile OpenCL kernel on command-line, creates sum.xclbin binary file 

​​xocc --xdevice xilinx:adm-pcie-7v3:1ddr:3.0 -t sw_emu -o sum.xclbin *.cl

​​# compile host code (only to check if flow works, want to use PyOpenCL eventually)

​​gcc -I/opt/Xilinx/SDAccel/2016.1/runtime/include host.c -L/opt/Xilinx/SDAccel/2016.1/runtime/lib/x86_64 -lxilinxopencl

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​​Update 5th August 2015 @4pm — Now the example Python code needs to be modified to load pre-compiled xclbin binary files… I tried to modify this as follows:

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​​dev =cl.get_platforms()[0].get_devices()

​​binary = open("sum.xclbin", "rb").read()