OpenCL is a great framework for developing parallel programs that work across multiple compatible accelerator-oriented platforms without source-level modifications. However, we find there are two main limitations that discourage adoption for newbies:
Host-side code — The C host program is responsible for managing data movement to/from the OpenCL accelerator as well as launch control of OpenCL code on the accelerator itself. This code tends to be verbose, confusing, and plain ugly. PyOpenCL provides a simple, elegant Python frontend to the OpenCL accelerator.
FPGA bitstream loading — When considering FPGA backends, we cannot really compile kernels on-the-fly in a reasonable amount of time. FPGA CAD tools are slow. This requires a different way of thinking about kernel launch. All kernels are precompiled into FPGA bitstreams and ready for loading prior to execution on the FPGA. Furthermore PyOpenCL does not have an obvious way to work with FPGA bitstreams forcing us to resort to the ugly C host-side programming.
Building a test program bitstream with aocl
Now, one would have thought running the Altera OpenCL compiler would be a piece of cake. One would be wrong. I had to add a couple of libraries to the path to make it work. Take care to ensure this only applies to your aocl call or you mess up other applications.
This attempt aims to enable FPGA support in PyOpenCL. We start by checking if straightforward device enumeration is possible using clinfo and then try meddling around with PyOpenCL code.
Listing OpenCL board information with clinfo
This is a handy utility that supports printing capabilities and specifications of all OpenCL compatible devices on your machine. Based on the source available at git@github.com:Oblomov/clinfo.git the compiled binary on Linux x86_64/Ubuntu 13.10 was only able to list Intel/NVIDIA devices. What’s the problem with listing FPGA cards? Turns out, the icd loading method doesn’t work with the FPGA OpenCL libraries. I believe this is due to the multiple .so files required to support FPGA cards, but that’s just a guess — one common OpenCL libalteracl.so from Altera, along with other .so files that are board-specific(built by Terasic in the case of DE5-NET card I have). Maybe this will all go away, if Altera just shipped an integrated shared object per FPGA board. So the only way to make this work for listing Altera devices is to change the Makefile(borrowed from the hello world example above)
This allowed me to list Altera devices when running clinfo. Here’s the attached log of the result(clinfo.txt) when running clinfo on a machine with the Altera DE5-NET FPGA card. When I remove the“-Wl,--no-as-needed” flag, I get an error again(clinfo_error.txt) which is remarkably similar to the one thrown by PyOpenCL shown below.
Error: Did not find any board vendor files in /opt/Altera/OpenCL/Boards/ to load board libraryat runtime. Either linkto the board librarywhile compiling your host code or refer to your board vendor's documentation on how to install the board library so that it can be loaded at runtime.
Warning: Cannot find any Altera board libraries. No Altera devices will be loaded.
Error: Could not load board libraries successfully.
Number of platforms 1
Error: Did not find any board vendor files in /opt/Altera/OpenCL/Boards/ to load board library at runtime. Either link to the board library while compiling your host code or refer to your board vendor's documentation on how toinstall the board library so that it can be loaded at runtime.
Warning: Cannot find any Altera board libraries. No Altera devices will be loaded.
Error: Could notload board libraries successfully.
main:2689: platform IDs : error-1001
Patching PyOpenCL to detect Altera boards
Out of the box, there are some stupid print() related error in compyte library that were incompatible with Python 3.3 syntax. Easy fix and move on(needed to add >> after each print call as its now a function()).
By default PyOpenCL does not enumerate any FPGA devices either. It uses the same standard approach based on icd files as clinfo(and I suspect all other OpenCL-compatible platforms). To trick it into recognizing the FPGA card we have to repeat the library paths fix as clinfo. With PyOpenCL this is embedded in the setup.py file.
Building a test program bitstream with aocl
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/opt/altera/16.0/quartus/dspba/backend/linux64/export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/lib/x86_64-linux-gnuaoc device/hello_world.cl -o bin/hello_world.aocx --board de5net_a7# compile aoc with emulation modeaoc -march=emulator device/hello_world.cl -o bin/hello_world.aocs --board de5net_a7# compile host program to generate a.outgcc `aocl compile-config` hello_world.c `aocl link-config`# run the host executable a.outCL_CONTEXT_EMULATOR_DEVICE_ALTERA=1 ./a.out bin/hello_world.aocxListing OpenCL board information with clinfo
LDLIBS=-lOpenCLLDLIBS=-L/opt/altera/16.0/hld/board/terasic/de5net/linux64/lib -L/opt/altera/16.0/hld/host/linux64/lib -Wl,--no-as-needed -lalteracl -lalterahalmmd -laltera_apb_14_0_mmdError: Did not find any board vendor files in /opt/Altera/OpenCL/Boards/ to load board library at runtime. Either link to the board library while compiling your host code or refer to your board vendor's documentation on how to install the board library so that it can be loaded at runtime.Warning: Cannot find any Altera board libraries. No Altera devices will be loaded.Error: Could not load board libraries successfully.Number of platforms 1Error: Did not find any board vendor files in /opt/Altera/OpenCL/Boards/ to load board library at runtime. Either link to the board library while compiling your host code or refer to your board vendor's documentation on how to install the board library so that it can be loaded at runtime.Warning: Cannot find any Altera board libraries. No Altera devices will be loaded.Error: Could not load board libraries successfully.main:2689: platform IDs : error -1001Patching PyOpenCL to detect Altera boards